DS31256 datasheet(69/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

69 of 183

7.2 HDLC Register Description

RHCDIS

Receive HDLC Channel Definition Indirect Select

0400h

Bit #

Name

HCID7

HCID6

HCID5

HCID4

HCID3

HCID2

HCID1

HCID0

Default

Bit #

Name

IAB

IARW

n/a

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)

00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0)

00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1)

00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2)

00000011 (03h) = HDLC channel number 4

11111111 (FFh) = HDLC channel number 256

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive HDLC

definition RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the

channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready

to be read from the RHCD register, the IAB bit is set to 0. When the host wishes to write data to the internal

receive HDLC definition RAM, the host should write this bit to 0. This causes the device to take the data that is

currently present in the RHCD register and write it to the channel location indicated by the HCID bits. When the

device completes the write, the IAB is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set

to 1. During a read operation, this bit sets to 1 until the data is ready to be read. It is set to 0 when the data is ready

to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write

operation completes.

RHCD

Receive HDLC Channel Definition

0404h

Bit #

Name

RABTD

RCS

RBF

RID

RCRC1

RCRC0

ROLD

RTRANS

Default

Bit #

Name

n/a

RZDD

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC controller performs flag

delineation, zero destuffing, abort detection, octet length checking (if enabled through ROLD), and FCS checking

(if enabled through RCRC0/1). When this bit is set high, the HDLC controller does not perform flag delineation,

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