DSP56166ROM datasheet(37/63 Pages) MOTOROLA

37 / 63 page

PRELIMINARY - 6/15/93

DSP56166 Technical Data Sheet

MOTOROLA

AC Electrical Characteristics — Bus Arbitration Timing — Slave Mode

VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125˚ C, CL = 50 pF + 1 TTL Load.

cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles

WS = Number of Wait States for X or P external memory , Determined by BCR or BCR2 Registers (WS = 0 to 31)

WT = WS*cyc=2T*WS

Wx = Number of Wait States for X external memory, Determined by BCR or BCR2 Registers (WS = 0 to 31)

Wp = Number of Wait States for P external memory, Determined by BCR Register (WS = 0 to 31)

Num

Characteristics

60 MHz

Unit

Min

Max

BR Input to CLKO low setup time

2.8

Delay from BR Input Assertion

(See note 1)

to BG Output Assertion

(See note 2)

(See note 3)

(See note 4)

(See note 5)

TBD

CLKO high to BG Output Assertion

7.2

BG Output Deassertion duration (See note 1)

for two consecutive BR

(See note 2)

(See note 3)

(See note 4)

(See note 5)

(See note 7)

TBD

—

CLKO High to Control Bus high impedance

TBD

CLKO High to BB Output Deassertion

10.3

CLKO High to BB Output (Three-state)

TBD

BR Input Deassertion to

(See note 1)

BG Output Deassertion

(See note 5)

(See note 7)

TBD

CLKO High to BG Deassertion

2.0

CLKO High to BB Output Active

TBD

CLKO High to BB Output Assertion

8.5

CLKO High to Address and Control Bus Active

TBD

CLKO High to Address and Control Bus Valid

8.5

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