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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56166ROM 데이터시트(PDF) 23 Page - Motorola, Inc |
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DSP56166ROM 데이터시트(HTML) 23 Page - Motorola, Inc |
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23 / 63 page  PRELIMINARY - 6/15/93 13 DSP56166 Technical Data Sheet MOTOROLA Clock Figure 1. External Clock Timing AC Electrical Characteristics — Other Clock and PLL Operation Timing Clock Figure 2. Clocking Configurations a. Maximum DSP operating frequency. See Operating Conditions. b. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level range (VILC>20% of Vdd or VIHC<70% of Vdd). Characteristics Min Max Unit PLL Output frequency 10 Max Fosca MHz EXTAL Input Clock Amplitude b 1 Vdd Vpp EXTAL PLL PLLE=1 PLLE=0 Fosc ID3-ID0 CLKO ÷ 2 internal phase PH0 at Fosc CS1-CS0 1000pF SXFC VDDS XFC1 0.01 µF GNDS 0.1 µF 100K Ω ÷ 1 to ÷ 16 VCO LF PFD YD7-YD0 ÷ 1 to ÷ 256 10nF Notes: 1. Must be a low leakage capacitor and must be located very close to the SXFC and VDDS pins. PD3-PD0 ÷ 20 to ÷ 215 PS=0 PS=1 |
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