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MSP432P411VIPZ 데이터시트(PDF) 153 Page - Texas Instruments |
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MSP432P411VIPZ 데이터시트(HTML) 153 Page - Texas Instruments |
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153 / 212 page ![]() 153 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V www.ti.com SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated (1) X = Don't care (2) Direction controlled by eUSCI_A1 module. (3) Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied. 6.12.2 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger Port Schematic: see Figure 6-8 Table 6-64 lists the settings to select the port functions. Table 6-64. Port P2 (P2.0 to P2.3) Pin Functions PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS (1) P2DIR.x P2SEL1.x P2SEL0.x P2MAPx P2.0/PM_UCA1STE/L11 0 P2.0 (I/O) I: 0; O: 1 0 0 X UCA1STE X (2) 0 1 default L11 (3) X 1 0 X N/A 0 1 1 X DVSS 1 P2.1/PM_UCA1CLK/L10 1 P2.1 (I/O) I: 0; O: 1 0 0 X UCA1CLK X (2) 0 1 default L10 (3) X 1 0 X N/A 0 1 1 X DVSS 1 P2.2/PM_UCA1RXD/PM_U CA1SOMI/L9 2 P2.2 (I/O) I: 0; O: 1 0 0 X UCA1RXD/UCA1SOMI X (2) 0 1 default L9 (3) X 1 0 X N/A 0 1 1 X DVSS 1 P2.3/PM_UCA1TXD/PM_U CA1SIMO/L8 3 P2.3 (I/O) I: 0; O: 1 0 0 X UCA1TXD/UCA1SIMO X (2) 0 1 default L8 (3) X 1 0 X N/A 0 1 1 X DVSS 1 |
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