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MSP432P411VIPZ 데이터시트(PDF) 87 Page - Texas Instruments

부품명 MSP432P411VIPZ
상세설명  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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MSP432P411VIPZ 데이터시트(HTML) 87 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
5.26.11 eUSCI
Table 5-39 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-39. eUSCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
VCORE
VCC
MIN
MAX
UNIT
feUSCI
eUSCI input clock frequency
Internal: SMCLK,
External: UCLK,
Duty cycle = 50% ±10%
1.2 V
12
MHz
1.4 V
24
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
1.2 V
5
MHz
1.4 V
7
Table 5-40 lists the characteristics of the eUSCI in UART mode.
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration must exceed the maximum
specification of the deglitch time.
Table 5-40. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tt
UART receive deglitch time(1)
UCGLITx = 0
5
20
ns
UCGLITx = 1
20
60
UCGLITx = 2
30
100
UCGLITx = 3
50
150
Table 5-41 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-41. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
feUSCI
eUSCI input clock frequency
SMCLK
Duty cycle = 50% ±10%
VCORE = 1.2 V
12
MHz
VCORE = 1.4 V
24



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