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MSP432P411VIPZ 데이터시트(PDF) 96 Page - Texas Instruments

부품명 MSP432P411VIPZ
상세설명  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

MSP432P411VIPZ 데이터시트(HTML) 96 Page - Texas Instruments

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TDO Output Valid
TCK
t
TDO_DV
TDO
TDI
TMS
TDI Input Valid
t
TDO_DVZ
t
TDI_SU
t
TDI_HLD
TMS Input Valid
t
TDI_SU
t
TDI_HLD
t
TDO_ZDV
t
TMS_HLD
t
TMS_SU
TMS Input Valid
TDI Input Valid
TDO Output Valid
t
TMS_HLD
t
TMS_SU
TCK
t
TCK_FALL
t
TCK_RISE
t
TCK_LOW
t
TCK_HIGH
t
TCK
96
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
5.26.14 Emulation and Debug
Table 5-52 lists the characteristics of the JTAG interface.
Table 5-52. JTAG
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
fTCK
TCK clock frequency
0
10
MHz
tTCK
TCK clock period
100
ns
tTCK_LOW
TCK clock low time
tTCK/2
ns
tTCK_HIGH
TCK clock high time
tTCK/2
ns
tTCK_RISE
TCK rise time
0
10
ns
tTCK_FALL
TCK fall time
0
10
ns
tTMS_SU
TMS setup time to TCK rise
30
ns
tTMS_HLD
TMS hold time from TCK rise
9
ns
tTDI_SU
TDI setup time to TCK rise
20
ns
tTDI_HLD
TDI hold time from TCK rise
7
ns
tTDO_ZDV
TCK fall to data valid from high impedance
9
44
ns
tTDO_DV
TCK fall to data valid from data valid
9
44
ns
tTDO_DVZ
TCK fall to high impedance from data valid
8
38
ns
Figure 5-74. JTAG Test Clock Input Timing
Figure 5-75. JTAG Test Access Port (TAP) Timing



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