MSP432P411VIPZ datasheet(195/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

6.14 Identification

6.14.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The

device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this

data sheet, see Section 8.4.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the Hardware Revision entry in the Device Descriptor structure (see

Section 6.13).

6.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific

errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see

Section 8.4.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For

details on this value, see the Device ID entry in the Device Descriptor structure (see Section 6.13).

6.14.3 Arm Cortex-M4F ROM Table Based Part Number

MSP432P4xx family of devices incorporate a part number for the device in addition to the device IDs

specified in the device descriptors (TLV) for the IDEs to recognize the device. This section describes how

this information is organized on the device.

The IEEE 1149.1 standard defines the use of a IDCODE register in the JTAG chain that provides the

fields in Table 6-90

Table 6-90. Structure of Device Identification Code

BIT POSITION

FIELD DESCRIPTION

31-28

Version

27-12

Part Number of the device

11-1

Manufacturer Identity

Reserved (Always tied to 1)

On MSP432P4xx devices all the fields in Table 6-90 are implemented on the Arm Cortex-M4 ROM table.

The part number can be read by the IDE tools to determine the device with which it is working.

Figure 6-24 shows the Peripheral ID register bit descriptions according to the Arm Cortex-M4

specifications.

Figure 6-24. Arm Cortex-M4 Peripheral ID Register Description

See the Arm Debug Interface V5 Architecture Specification for bit-level details on the Arm Cortex-M4

Peripheral ID registers.

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