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SLG46121V 데이터시트(PDF) 72 Page - Dialog Semiconductor

부품명 SLG46121V
상세설명  Personal Computers and Servers
PDF  98 Pages
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Page 71 of 97
SLG46121
12.2 CNT/DLY1 Register Settings
Table 54. CNT/DLY1 Register Settings
Signal Function
Register Bit
Address
Register Definition
Counter/Delay1
Mode Select
reg <568>
0: Delay Mode
1: Counter Mode
Counter/Delay1
Clock Source Select
(external clock is
only for counter
mode)
reg <571:569>
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: Reserved
111: Counter0 Overflow
Counter1 Control
Data/Delay1 Time
Control
reg <579:572>
1-256: (delay time = (counter control data +2) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg <581:580>
00: Delay on both falling and rising edges (for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode



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