SLG46121V datasheet(76/98 Pages) DIALOG

76 / 98 page

000-0046121--106

Page 75 of 97

SLG46121

The user can select one of these fundamental frequencies for the RC OSC Macrocell, or the fundamental frequency can also

come from an external clock input (Pin 12). There are two divider stages that allow the user flexibility for introducing clock signals

on various Connection Matrix Input lines. The first stage divider (also known as the clock pre-divider) allows the selection of /1,

/2, /4 or /8 divide down frequency from the fundamental. There are two second stage divider controls (OUT0 and OUT1). Each

has its own input of one frequency from the first stage divider, and outputs two different frequencies on Connection Matrix Input

lines <30>, and <31>. See Figure 48 below for details of the frequencies for each of these two Connection Matrix Inputs.

If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator

will be turned off. The PWR DOWN signal has the highest priority.

14.2 RC OSC Block Diagram

Figure 48. RC OSC Block Diagram

Internal RCO

reg <536>

0: 25 kHz

1: 2 MHz

/ 2

/ 3

/ 4

/ 8

/ 12

/ 24

/ 64

To Connection Matrix Input <30>

reg <541:539>

DIV /1/2/4/8

reg <538:537>

Clock Pre- Divider

Control

Second Stage

Divider

Pin 12 Ext. Clock

Ext. Clk Sel reg <545>

reg <544:542>

To Connection Matrix Input <31>

From Connection Matrix Output <59>

PWR DOWN

OUT0

OUT1

SLG46121V 데이터시트(PDF) 76 Page - Dialog Semiconductor