Data Sheet

AD8285

Rev. B | Page 25 of 27

APPLICATION DIAGRAMS

The typical application diagrams for the AD8285 are shown in Figure 33 and Figure 34. As discussed in the Channel Overview section,

the maximum signal swing and the minimum third-order distortion can be achieved when the AD8285 is driven with a fully differential

source. The typical connections for this configuration are shown in Figure 33.

Figure 33. Differential Inputs Application Diagram

CLK+

CLK–

PDWN

SCLK

SDIO

AUX

MUXA

ZSEL

DSYNC

NOTES

1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES MUST BE PLACED CLOSE TO THE DEVICE.

3.3V

AVDD33REF

0.1µF

AVDD33A

0.1µF

AVDD33B

0.1µF

AVDD33C

0.1µF

AVDD33D

0.1µF

AVDD33

0.1µF

3.3V

DVDD33SPI

0.1µF

DVDD33CLK

0.1µF

DVDD33DRV

0.1µF

DVDD33DRV

0.1µF

1.8V

AVDD18

0.1µF

AVDD18

0.1µF

AVDD18ADC

0.1µF

1.8V

DVDD18

0.1µF

DVDD18CLK

0.1µF

INC+

0.1µF

INC–

0.1µF

INB+

0.1µF

INB–

0.1µF

0.1µF

INA+

0.1µF

INA–

INADC+

0.1µF

0.1µF

0.1µF

10kΩ

1%

10kΩ

INADC–

0.1µF

IND–

0.1µF

IND+

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

NC

NC

DSYNC

PDWN

DVDD18

SCLK

SDIO

CS

AUX

MUXA

ZSEL

TEST1

TEST2

DVDD33SPI

AVDD18

AVDD33A

INA–

17

INA+

18

NC

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

NC

TEST4

DVDD18CLK

CLK+

CLK–

DVDD33CLK

AVDD33REF

VREF

RBIAS

BAND

APOUT

ANOUT

TEST3

AVDD18ADC

AVDD18

INADC+

INADC–

NC

AD8285

TOP VIEW

(Not to Scale)

CS