AD8285

Data Sheet

Rev. B | Page 20 of 27

Figure 32. Serial Timing Details

Table 8. Serial Timing Definitions

Parameter

Minimum Timing (ns)

Description

5

Setup time between the data and the rising edge of SCLK

2

Hold time between the data and the rising edge of SCLK

40

Period of the clock

5

Setup time between CS and SCLK

2

Hold time between CS and SCLK

16

Minimum period that SCLK should be in a logic high state

16

Minimum period that SCLK should be in a logic low state

10

Minimum time for the SDIO pin to switch from an input to an output relative to the

SCLK falling edge (not shown in Figure 32)

10

Minimum time for the SDIO pin to switch from an output to an input relative to the

SCLK rising edge (not shown in Figure 32)

DON’T CARE

DON’T CARE

DON’T CARE

DON’T CARE

SDIO

SCLK

CS

R/W

W1

W0

A12

A11

A10

A9

A8A7

D5D4D3

D2

D1D0