BLUENRG-2 datasheet(128/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

selected for TnCNT2. Thus, it is possible to determine the number of capture events on

TnB or the elapsed time between capture events on TnB by using TnCNT2.

3.13.2.4

MFT mode 3: dual independent timer/counter mode

This Mode3 allows using the two Timer/Counter 1 and 2 separately.

The Timer/Counter1 can be used:



As a system counter: to count down at the rate of the selected clock.



To generate a 50% duty-cycle clock signal on TnA pin connected to the PWMx pin of

the device (TnCNT1 reloaded by TnCRB on underflow).



To be an event counter using TnB pin as an external event or pulse-accumulate input.

The Timer/Counter2 can be used:



As a system counter: to count down at the rate of the selected clock.



To be an event counter using TnB pin as an external event or pulse-accumulate input.

In figure below the block diagram related to the MFT mode 3.

Figure 19: MFT mode 3 block diagram

In Mode 3, the timer/counter is configured to operate as a dual independent system timer

or dual external-event counter. In addition, Timer/Counter 1 can generate a 50% duty cycle

PWM signal on the TnA pin. The TnB pin can be used as an external-event input or pulse-

accumulate input, and serve as the clock source to either Timer/Counter 1 or

Timer/Counter 2. Both counters can also be operated from the prescaled system clock.

Timer/Counter 1 (TnCNT1) counts down at the rate of the selected clock. Upon underflow,

TnCNT1 is reloaded from the TnCRB register and counting proceeds. If enabled, the TnA

pin toggles upon underflow of TnCNT1. The initial value of the TnA output can be selected

by software to be either high or low. In addition, the TnAPND interrupt-pending flag is set,

and a timer interrupt 1 is generated if the TnAIEN bit is set. Since TnA toggles upon every

underflow, a 50% duty-cycle PWM signal can be generated on TnA without requiring any

interaction of the software or the CPU.

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