L9678P datasheet(119/203 Pages) STMICROELECTRONICS

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L9678P, L9678P-S

Deployment drivers

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Values of each measurement step can be required addressing the proper ADCREQx code

in the Diagnostic Control command (DIAGCTRL) on Table 11: Diagnostics control register

(DIAGCTRLx) on page 159.

This calculation is tolerant to leakages and, thanks to a dedicated EMI low-pass filter, also to

high frequency noises on squib lines. Moreover, L9678P features a slew rate control on the

ISRC current generator to mitigate emissions.

High squib resistance diagnostics

With this test, the device is able to understand if the squib resistance value is below 200 Ω,

between 500 Ω and 2000 Ω or beyond 5000 Ω. During a high squib resistance diagnostics,

VRCM and ISNK are enabled and connected respectively to SFx and SRx on the selected

channel. VREF voltage level outputs on SFx. Current flowing on SFx is measured and

compared to ISRlow and ISRhigh thresholds to identify if the resistance is above or below

RSRlow or RSRhigh levels. The results are reported in the LPDIAGSTAT register. The relative

flags (HSR_HI and HSR_LO) are not latched and reflect the current status of the

comparators.

High and low side FET diagnostics

This couple of tests can only be run during the diagnostic mode of the power-up sequence

(Figure 9). Tests are performed individually for HS driver or LS driver, with two dedicated

commands. Prior to either the HS or LS FET diagnostics being run, the VRCM has to be first

enabled. Within the command to enable the VRCM, also the channel onto which the FET

test will be run has to be selected with the LEAK_CHSEL bit field. Running the leakage

diagnostics with the appropriate delay time prior to either the HS or LS FET diagnostics will

precondition the squib pin to the appropriate voltage level. When the FET diagnostic

command is issued with the Diagnostic Register SPI command (SYSDIAGREQ), the VRCM

flags will be cleared.

The device monitors the current through the VRCM. If the FET is working properly, this

current will exceed ISTB (HS test) or ISTG (LS test) and the driver under test is turned off

immediately. If the current does not exceed ISTB or ISTG then the test will be terminated and

the output is anyway turned off within TFETTIMEOUT. During TFETTIMEOUT period, the bit

stating that the FET is enabled will be set (FETON=1) and will be cleared as soon as the

FET is switched back off.

For all conditions the current on SFx/SRx will not exceed ILIM_VRCM_X, the VRCM block

current limitation value. There may be higher currents on the squib lines due to the presence

of filter capacitors. During these FET tests, energy available to the squib is limited to less

than EFETtest.

For high side FET diagnostics, if no faults were indicated in the preceding leakage

diagnostics then a normal result would be [STB=1, STG=0]. If the returned result for the

high side FET test is not as the previous then either the FET is not functional, a short to

ground occurred during the test, or there is a missing SSxy connection for that channel.

For low side FET diagnostics if no faults were indicated in the preceding leakage

diagnostics then a normal result would be [STB=0, STG=1]. If the returned result for the low

side FET test is not as the previous one then either the FET is not functional or a short to

battery occurred during the test. In case of SGx loss the low-side FET diagnostic would not

indicate a FETfault.

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