L9678P datasheet(36/203 Pages) STMICROELECTRONICS

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SPI interface

L9678P, L9678P-S

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DocID029274 Rev 3

SPI interface

The L9678P system solution device has many user selectable features controlled through

serial communications by the integrated microcontroller. The SPI interface provides

configuration, control and status functions for the device. The global SPI interface consists

of an input shift register, output shift register and four control signals. SPI_MOSI is the data

input to the input shift register. SPI_MISO is the data output from the output shift register.

SPI_SCK is the clock source input while SPI_CS is the active-low chip select input.



All SPI communications are executed in exact 32 bit increments. The general format of the

32 bit transmission is shown in Table 5.

Data to the IC (i.e. SPI_MOSI) consists of a target read register ID (RID), a target write

data to be written to the target write register indicated by WID. Data returned from the IC

(i.e. SPI_MISO) consists of a global status word (GSW), read data parity (RPAR) and 20 bits

of data (READ). READ data will be the contents of the target read register as indicated by

the RID bits. The parity bits WPAR and RPAR cover all the 32 bits of the MOSI and MISO

frames, respectively. Odd parity type is used.

The communications is controlled through SPI_CS, enabling and disabling communication.

When SPI_CS is at logic high, all SPI communication I/O is tri-stated and no data is

accepted. When SPI_CS is low, data is latched on the rising edge of SPI_SCK and data is

shifted on the falling edge. The SPI_MOSI pin receives serial data from the master with

MSB first. Likewise for SPI_MISO, data is read MSB first, LSB last.

The L9678P IC contains a data validation method through the SPI_SCK input to keep

transmissions with not exactly 32 bits from being written to the device. The SPI_SCK input

counts the number of received clocks and should the clock counter exceed or count fewer

than 32 clocks, the received message is discarded and a SPI_FLT bit is flagged in the

Global Status Word (GSW). The SPI_FLT bit is also set in case of parity error detected on

the MOSI frame. Any attempt access to a register with a forbidden access mode (read or

write) is not leading to changes to the internal registers but the SPI_FLT bit is not set in this

case.

The SPI interface consists of several 32-bit registers to allow for configuration, control and

status of the IC as well as special manufacturing test modes. The register definition is

defined by the read register ID (RID) and the write register ID (WID) as shown in Table 6 -

Global SPI Register Table. Global ID bit (GID) is used to extend available register

addresses, but it is shared between RID and WID; only RID and WID with the same GID

value can be addressed within the same SPI word. The operating states here show in which

states the SPI write command is processed.

Table 5. SPI register R/W

SPI register R/W

SPI_MOSI

GID

RID[6:0]

WID[6:0]

WPAR

SPI_MISO

GSW[10:0]

RPAR

READ[19:16]

SPI_MOSI

WRITE[15:0]

SPI_MISO

READ[15:0]

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