G52154-0, Rev 4.2

© VITESSE SEMICONDUCTOR CORPORATION

Page 13

3/19/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8113

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Latency

The VSC8113 contains several operating modes, each of which exercise different logic paths through the

part. Table 10 bounds the data latency through each path with an associated clock signal.

Table 10: Data Latency

Clock Recovery Unit

Table 11: Reference Frequency for the CRU

Clock Multiplier Unit

Table 12: Reference Frequency Selection and Output Frequency Control

Circuit Mode

Description

Clock

Reference

Range of Clock

cycles

Transmit

Data TXIN [7:0] to MSB at TXDATAOUT

TXCLKOUT

4-13

Receive

MSB at RXDATAIN to data on RXOUT [7:0]

RXCLKIN

25-35

Equipment

Loopback

Byte data TXIN [7:0] to byte data on RXOUT [7:0]

TXCLKOUT

27-35

Facilities

Loopback

MSB at RXDATAIN to MSB at TXDATAOUT

RXCLKIN

2-4

CRUREFSEL

STS12

B2

B1

B0

CRUREFCLK

Frequency

[MHz]

Output

Frequency

[MHz]

11

X

X

X

77.76 ± 500ppm

622.08

1

0

X

X

X

77.76 ± 500ppm

155.52

0

Uses CMU’s Reference Clock (See Table 12 below)

STS12

B2

B1

B0

Reference

Frequency

[MHz]

Output

Frequency

[MHz]

1110

19.44

622.08

1010

38.88

622.08

1001

51.84

622.08

1000

77.76

622.08

0110

19.44

155.52

0010

38.88

155.52

0001

51.84

155.52

0000

77.76

155.52