PC755CMZFU366LE datasheet(10/50 Pages) ATMEL

10 / 50 page

PC755/745

2138D–HIREL–06/03

Table 2 provides the pinout listing for the PC755, 360 PBGA, CBGA and CI-CGA + HiTCE

Table 2. Pinout Listing for the PC755, 360 PBGA, CBGA and CI-CGA Packages + HiTCE

(8)

Signal Name

Pin Number

Active

I/O

I/F Voltages

Supported(1)

1.8V/2.0V

3.3V

A[0

-31]

A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2,

E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2,

High

I/O

–

AACK

Low

Input

–

ABB

Low

I/O

–

AP[0

-3]

C4, C5, C6, C7

High

I/O

–

ARTRY

Low

I/O

–

AVDD

Low

Input

–

Low

Output

–

BVSEL(3)(5)(6)

High

Input

GND

3.3V

Low

Output

–

CKSTP_IN

Low

Input

–

CKSTP_OUT

Low

Output

–

CLK_OUT

–

Output

–

DBB

Low

I/O

–

DBDIS

Low

Input

–

DBG

Low

Input

–

DBWO

Low

Input

–

DH[0

-31]

W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9,

R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4,

W3, U4, R5

High

I/O

–

DL[0

-31]

M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,

W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2,

V3, U3, W2

High

I/O

–

DP[0

-7]

L1, P2, M2, V2, M1, N2, T3, R1

High

I/O

–

DRTRY

Low

Input

–

GBL

Low

I/O

–

GND

D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11,

H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16,

L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16,

R8, R12, T4, T6, T10, T14, T16

–

GND

HRESET

Low

Input

–

INT

C11

Low

Input

–

L1_TSTCLK(2)

High

Input

–

L2ADDR[0

-16]

L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17,

J14, J13, H19, G18

High

Output

–

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