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PC755CMZFU366LE 데이터시트(PDF) 48 Page - ATMEL Corporation |
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PC755CMZFU366LE 데이터시트(HTML) 48 Page - ATMEL Corporation |
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48 / 50 page ![]() 48 PC755/745 2138D–HIREL–06/03 In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k Ω – 5 kΩ) if it is used by the system. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the processor must continually monitor these signals for snooping, this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system. These signals can be pulled up through weak (10 k Ω) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be other- wise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise nor- mally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all par- ity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. Definitions Datasheet Status Validity Objective specification This datasheet contains target and goal specification for discussion with customer and application validation. Before design phase. Target specification This datasheet contains target or goal specification for product development. Valid during the design phase. Preliminary specification ∝ site This datasheet contains preliminary data. Additional data may be published later; could include simulation result. Valid before characterization phase. Preliminary specification β site This datasheet contains also characterization results. Valid before the industrialization phase. Product specification This datasheet contains final product specification. Valid for production purpose. Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. |
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