PIC18F4539-ESLASHMLSQTP datasheet(210/322 Pages) MICROCHIP

210 / 322 page

PIC18FXX39

DS30485A-page 208

Preliminary

 2002 Microchip Technology Inc.

20.4.1

PROGRAM MEMORY

CODE PROTECTION

The user memory may be read to, or written from, any

location using the Table Read and Table Write instruc-

tions. The device ID may be read with Table Reads.

The configuration registers may be read and written

with the Table Read and Table Write instructions.

In User mode, the CPn bits have no direct effect. CPn

bits inhibit external reads and writes. A block of user

memory may be protected from Table Writes if the

WRTn configuration bit is ‘0’. The EBTRn bits control

Table Reads. For a block of user memory with the

EBTRn bit set to ‘0’, a Table Read instruction that exe-

cutes from within that block is allowed to read. A Table

Read instruction that executes from a location outside

of that block is not allowed to read, and will result in

reading ‘0’s. Figures 20-4 through 20-6 illustrate Table

Write and Table Read protection.

FIGURE 20-4:

TABLE WRITE (WRTn) DISALLOWED

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection bits are only set to ‘1’ by a block

erase function. The block erase function

can only be initiated via ICSP or an

external programmer.

000000h

0001FFh

000200h

001FFFh

002000h

003FFFh

004000h

005FFFh

WRTB,EBTRB = 11

WRT0,EBTR0 = 01

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

TBLWT *

TBLPTR = 000FFF

PC = 001FFE

TBLWT *

PC = 004FFE

Program Memory

Configuration Bit Settings

Results: All Table Writes disabled to Blockn whenever WRTn = 0

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