PIC18F4539-ESLASHMLSQTP datasheet(74/322 Pages) MICROCHIP

74 / 322 page

PIC18FXX39

DS30485A-page 72

Preliminary

 2002 Microchip Technology Inc.

INTCON2 REGISTER

R/W-1

U-0

R/W-1

U-0

R/W-1

RBPU

INTEDG0

INTEDG1

INTEDG2

—TMR0IP

—RBIP(1)

bit 7

bit 0

bit 7

RBPU: PORTB Pull-up Enable bit

= All PORTB pull-ups are disabled

= PORTB pull-ups are enabled by individual port latch values

bit 6

INTEDG0: External Interrupt 0 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 5

INTEDG1: External Interrupt 1 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 4

INTEDG2: External Interrupt 2 Edge Select bit

= Interrupt on rising edge

= Interrupt on falling edge

bit 3

Unimplemented: Read as '0'

bit 2

TMR0IP(1): TMR0 Overflow Interrupt Priority bit

= High priority

= Low priority

bit 1

Unimplemented: Read as '0'

bit 0

RBIP(1): RB Port Change Interrupt Priority bit

= High priority

= Low priority

Note 1: Maintain this bit cleared (= 0).

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

PIC18F4539-E/MLSQTP 데이터시트(PDF) 74 Page - Microchip Technology

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