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PIC18F4539-E/MLSQTP 데이터시트(PDF) 76 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP 데이터시트(HTML) 76 Page - Microchip Technology |
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76 / 322 page ![]() PIC18FXX39 DS30485A-page 74 Preliminary 2002 Microchip Technology Inc. 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag registers (PIR1, PIR2). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. R/W-0 R/W-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF —TMR2IF(2) TMR1IF bit 7 bit 0 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit (see Section 17.0 for details on TXIF functionality) 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF(2): TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = MR1 register did not overflow Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear. 2: This bit is reserved for use by the ProMPT kernel; do not alter its value. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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