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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC18F4539-E/MLSQTP 데이터시트(PDF) 147 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP 데이터시트(HTML) 147 Page - Microchip Technology |
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147 / 322 page  2002 Microchip Technology Inc. Preliminary DS30485A-page 145 PIC18FXX39 16.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to ‘0’. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12). FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING SDA SCL DX-1 DX WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPCON CKP Master device de-asserts clock Master device asserts clock |
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