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CYUSB302X 데이터시트(PDF) 16 Page - Cypress Semiconductor

부품명 CYUSB302X
상세설명  SD3??USB and Mass Storage Peripheral Controller
PDF  34 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYUSB302X 데이터시트(HTML) 16 Page - Cypress Semiconductor

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Document Number: 001-55190 Rev. *L
Page 16 of 34
CYUSB302x
tSDOH CMD
Host output hold time for CMD
3
–
ns
tSDOH DAT
Host output hold time for DAT
3
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
19.2
–
ns
SDFREQ
Clock frequency
–
52
MHz
tSDCLKOD
Clock duty cycle
40
60
%
MMC-DDR52
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
0.56
–
ns
tSDIH CMD
Host input hold time for CMD
3
–
ns
tSDIH DAT
Host input hold time for DAT
2.58
–
ns
tSDOS CMD
Host output setup time for CMD
3
–
ns
tSDOS DAT
Host output setup time for DAT
2.5
–
ns
tSDOH CMD
Host output hold time for CMD
3
–
ns
tSDOH DAT
Host output hold time for DAT
2.5
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
19.2
–
ns
SDFREQ
Clock frequency
52
MHz
tSDCLKOD
Clock duty cycle
45
55
%
SD-Default Speed (SDR12)
tSDIS CMD
Host input setup time for CMD
24
–
ns
tSDIS DAT
Host input setup time for DAT
24
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
tSDOS CMD
Host output setup time for CMD
5
–
ns
tSDOS DAT
Host output setup time for DAT
5
–
ns
tSDOH CMD
Host output hold time for CMD
5
–
ns
tSDOH DAT
Host output hold time for DAT
5
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
40
–
ns
SDFREQ
Clock frequency
25
MHz
tSDCLKOD
Clock duty cycle
40
60
%
SD-High-Speed(SDR25)
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
4
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
Table 9. S-Port Timing Parameters[3] (continued)
Parameter
Description
Min
Max
Units



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