CYUSB302X datasheet(26/34 Pages) CYPRESS

26 / 34 page

Document Number: 001-55190 Rev. *L

Page 26 of 34

CYUSB302x

Reset Sequence

Table 14 provides the hard reset sequence requirements for SD3.

Figure 7. Reset Sequence

Table 14. Reset and Standby Timing Parameters

Parameter

Definition

Conditions

Min (ms)

Max (ms)

tRPW

Minimum RESET# pulse width

Clock Input

–

Crystal Input

–

tRH

Minimum high on RESET#

–

tRR

Reset Recovery Time (after which Boot loader begins

firmware download)

Clock Input

–

Crystal Input

tSBY

Time to enter Standby/Suspend (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

–

tWU

Time to wakeup from standby

Clock Input

–

Crystal Input

–

tWH

Minimum time before Standby/Suspend source may be

reasserted

–

VDD

(core )

xVDDQ

XTALIN/

CLKIN

RESET #

Mandatory

Reset Pulse

Hard Reset

tRPW

tRh

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit

is set)

Standby/Suspend

source Is deasserted

tSBY

tWU

XTALIN/ CLKIN must be stable

before exiting Standby/Suspend

tRR

tWH

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