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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MB91F585ASH 데이터시트(PDF) 142 Page - Cypress Semiconductor |
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MB91F585ASH 데이터시트(HTML) 142 Page - Cypress Semiconductor |
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142 / 176 page  Document Number: 002-04665 Rev *A Page 141 of 175 MB91580M/S Series Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "L" (SMR:SCINV=1) (TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3* Master mode CL=50pF 4tCPP - ns SCK ↑ ⇒ SOT delay time tSHOVI SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3*, SOT0_0, SOT0_1 *, SOT1, SOT2 *, SOT3* -30 +30 ns Valid SIN ⇒ SCK ↓ setup time tIVSLI SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3*, SIN0_0, SIN0_1 *, SIN1, SIN2 *, SIN3* 30 - ns SCK ↓ ⇒ Valid SIN hold time tSLIXI 0 - ns Serial clock "H"pulse width tSHSL SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3* Slave mode CL=50pF tCPP+10 - ns Serial clock "L"pulse width tSLSH 2tCPP-10 - ns SCK ↑ ⇒ SOT delay time tSHOVE SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3*, SOT0_0, SOT0_1 *, SOT1, SOT2 *, SOT3* - 30 ns Valid SIN ⇒ SCK ↓ setup time tIVSLE SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3*, SIN0_0, SIN0_1 *, SIN1, SIN2 *, SIN3* 10 - ns SCK ↓ ⇒ Valid SIN hold time tSLIXE 20 - ns SCK fall time tF SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3* - 5 ns SCK rise time tR SCK0_0, SCK0_1 *, SCK1, SCK2 *, SCK3* - 5 ns *: Only available with MB91F583AM/F584AM/F585AM Notes: This is the AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operation clock used and other parameters. See Hardware Manual for details. |
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