MB91F522DKBPMC datasheet(47/280 Pages) CYPRESS

47 / 280 page

Document Number: 002-04662 Rev. *F

Page 47 of 280

MB91520 Series

Block Diagram

MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B

From Master

To Slave

From Master

To Slave

XBS Crossbar Switch

FR81s CPU core

Instruction

Data

On-chip bus layer 2

Peripheral Bus

Bridge

CAN prescaler

Watchdog timer(SW and HW)

Delay interrupt

Interrupt controller

RTC／WDT1 Calibration

Ｉ/Ｏ port setting

Low-power consumption setting register

Wild register

On-chip bus layer 1

Debug

Interface

Regulator

Interrupt request batch read

DMA transfer request generate/clear

Real time clock

Clock supervisor

Clock control （Clock setting,

Main timer, Sub timer, PLL timer）

M P U

Clock control （divide control）

Bus

performance

counter

BackUp

RAM +8KB

Timing

Protection Unit

PPG(21ch)

Reload timer (7ch)

8bit DA converter (1ch)

External interrupt input(16ch)

32bit Output compare(4ch)

Base timer (1ch)

U/D counter (2ch)

32bit Free-run timer(1ch)

32bit Input capture(5ch)

Multi-function serial interface (8ch)

DMAC

(16 ch)

CAN (3ch)

CRC

Operation mode

Wave generator (6ch)

12bit AD converter (13ch + 13ch)

16bit Free-run timer (3ch)

16bit Input capture (4ch)

Power-on reset

CR oscillator

Low-voltage detection

（External power supply low-voltage detection）

Reset control register

NMI

Flash

・Main Flash

256K/384K/512K/768K/

1024KB +64KB

RAM

48K/64K/96K/128K

Clock monitor

Bus Bridge (32bit <-> 16bit)

RAM ECC Control(XBS RAM)

Clock /

Bus Bridge

RAM ECC Control

(BackUp RAM)

Async Bus Bridge (PCLK1 <-> PCLK2)

Bus Bridge (32bit <-> 16bit)

16bit Output compare (6ch)

Async Bus Bridge (PCLK1 <-> PCLK2)

Low-voltage detection

（Internal power supply low-voltage detection）

RST

NMIX

MD0,MD1,P00

RX,T

FRCK

ICU

OCU

TIOA,TIOB

AIN,BIN,ZI

TIN,TOT

DAO

MONCLK

WOT

INT

TRG,PPG

SOUT,

SIN,

SCK

ADTG,AIN

ICU

FRCK

DTTI,RTO

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