MB91F522DKBPMC datasheet(51/280 Pages) CYPRESS

51 / 280 page

Document Number: 002-04662 Rev. *F

Page 51 of 280

MB91520 Series

MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K

From Master

To Slave

From Master

To Slave

XBS Crossbar Switch

FR81s CPU core

Instruction

Data

On-chip bus layer 2

External Bus

I / F

Peripheral Bus

Bridge

CAN prescaler

Watchdog timer(SW and HW)

Delay interrupt

Interrupt controller

RTC／WDT1 Calibration

Ｉ/Ｏ port setting

Low-power consumption setting register

Wild register

On-chip bus layer 1

Debug Interface

Regulator

Interrupt request batch read

DMA transfer request generate/clear

Real time clock

Clock supervisor

Clock control （Clock setting,

Main timer, Sub timer, PLL timer）

M P U

Clock control （divide control）

Bus

performance

counter

BackUp

RAM +8KB

Timing Protection

Unit

PPG(44ch)

Reload timer (8ch)

8bit DA converter (2ch)

External interrupt input(16ch)

32bit Output compare(6ch)

Base timer (2ch)

U/D counter (2ch)

32bit Free-run timer(3ch)

32bit Input capture(6ch)

Multi-function serial interface (12ch)

DMAC

(16 ch)

CAN (3ch)

CRC

Operation mode

Wave generator (6ch)

12bit AD converter (32ch + 16ch)

16bit Free-run timer (3ch)

16bit Input capture (4ch)

Power-on reset

CR oscillator

Low-voltage detection

（External power supply low-voltage detection）

Reset control register

NMI

Flash

・Main Flash 256K/384K/512K/768K/

1024KB +64KB

・WorkFlash 64KB

RAM

48K/64K/96K/128K

Clock monitor

Bus Bridge (32bit <-> 16bit)

RAM ECC Control(XBS RAM)

Clock / Bus

Bridge

RAM ECC Control

(BackUp RAM)

Async Bus Bridge (PCLK1 <-> PCLK2)

16bit Output compare (6ch)

Async Bus Bridge (PCLK1 <-> PCLK2)

Low-voltage detection

（Internal power supply low-voltage detection）

RSTX

NMIX

MD0,MD1,P006

RX,TX

D,A,

ASX,CS,

RDX,

WRX,

SYSCLK,

RDY

FRCK

ICU

OCU

TIOA,TIOB

AIN,BIN,ZIN

TIN,TOT

DAO

MONCLK

WOT

INT

TRG,PPG

SOUT,

SIN,

SCK

ADTG,AIN

ADC enable(ADER)

ICU

FRCK

DTTI,RTO

Bus Bridge (32bit <-> 16bit)

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