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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MB91F522DKBPMC 데이터시트(PDF) 184 Page - Cypress Semiconductor |
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MB91F522DKBPMC 데이터시트(HTML) 184 Page - Cypress Semiconductor |
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184 / 280 page  Document Number: 002-04662 Rev. *F Page 184 of 280 MB91520 Series (11) External bus I/F (asynchronous mode) timing (TA: -40 °C to +105 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) (external load capacitance 50pF) Parameter Symbol Pin Name Value Unit Remarks Min Max Cycle time tCYC SYSCLK 25 - ns VCC = 5.0 V ± 10 %*1 31.25 VCC = 3.3 V ± 0.3 V Address setup → RDX↑time tASRH RDX A00 to A21 2×tCYC - 12 2×tCYC + 12 ns RWT = 1, set RWT to 1 or more. *2 RDX↑→ Address hold tRHAH tCYC - 12 tCYC + 12 ns Set RDCS to 1 or more. Data setup → RDX↑time tDSRH RDX D16 to D31 18 + tCYC - ns RWT = 1, set RWT to 1 or more. RDX↑→ Data hold tRHDH 0 - ns Address setup → WRnX↑time tASWH WR0X to WR1X A00 to A21 tCYC - 12 tCYC + 12 ns WWT = 0 *2 WRnX↑→ Address hold tWHAH tCYC - 12 tCYC + 12 ns Set WRCS to 1 or more. Data setup → WRnX↑time tDSWH WR0X to WR1X D16 to D31 tCYC - 16 tCYC + 16 ns WWT = 0 *2 WRnX↑→ Data hold tWHDH tCYC - 16 tCYC + 16 ns Set WRCS to 1 or more. Address setup → ASX↑time tMASASH ASX D16 to D31 tCYC-16 tCYC+ 16 ns ASCY = 0 ASX↑→Address hold tMASHAH tCYC-16 tCYC + 16 ns In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because of setting ADCY > ASCY and protocol violation prevention. ADCY +1 ≤ ACS + CSRD ADCY +1 ≤ ACS + CSWR ASCY + 1 ≤ ACS + CSRD ASCY + 1 ≤ ACS + CSWR See Hardware Manual for details. *1: Please use it with external load capacity 12 pF or less for VCC = 3.3 V ± 0.3 V (40 MHz operation). *2: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. |
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