5222-DS02-R datasheet(48/76 Pages) BOARDCOM

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BCM5222

Preliminary Data Sheet

7/20/04

Broadcom Corporation

Page 36

Auxiliary Mode 2 Register

Document 5222-DS02-405-R

SPD MASK

When this bit is set, changes in operating speed will not generate a a hardware or software interrupt.

LINK MASK

When this bit is set, changes in Link status will not generate a a hardware or software interrupt.

INTERRUPT MASK

Master Interrupt Mask. When this bit is set, no interrupts will be hardware generated, regardless of the state of the other

MASK bits.

FDX CHANGE

A “1” indicates a change of Duplex status since last register read. register read clears the bit.

SPD CHANGE

A “1” indicates a change of Speed status since last register read. register read clears the bit.

LINK CHANGE

A “1” indicates a change of Link status since last register read. register read clears the bit.

INTERRUPT STATUS

Represents status of the INTR pin. A “1” indicates that the Interrupt Mask is off and that one or more of the change bits are

set. A register read clears the bit.

AUXILIARY MODE 2 REGISTER

Table 22: Auxiliary Mode 2 Register (Address 27d, 1Bh)

BIt

Name

R/W

Description

Default

15:12

Reserved

Ignore when read

10BT Dribble Bit Correct

R/W

1 = Enable, 0 = Disable

Jumbo Packet Enable

R/W

1 = Enable, 0 = Disable

Reserved

R/W

Write as 0, Ignore when read

TXC Invert

R/W

1= invert clock

Block 10BT Echo Mode

R/W

1 = Enable, 0 = Disable

6:4

Reserved

R/W

Write as 0, Ignore when read

000

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