CS43L36 datasheet(36/89 Pages) CIRRUS

36 / 89 page

DS1081F3

CS43L36

4.5 Audio Serial Port (ASP)

Figure 4-17. ASP LRCK Period, High Width, 50/50 Mode

Fig. 4-18 shows how LRCK frame start delay (ASP_FSD, see p. 66) controls the number of SCLK periods from LRCK

synchronization edge to the start of frame data.

4.5.3

Channel Location and Resolution

Each serial-port channel’s location and offset is configured through the registers in Table 4-7. Location is programmable

in single SCLK-period resolution. If set to the minimum location offset, a channel sends or receives on the first SCLK period

of a new frame. Channel size is programmable in 8- to 32-bit byte resolutions. DAC ports are limited to 24 bits and truncate

the 8 LSBs of a 32-bit audio stream.

Channel size and location must not be programmed such that channel data exceeds the frame boundary. In other words,

channel size and offset must not exceed the expected SCLK per LRCK settings. Size and location must not be

Figure 4-18. LRCK Frame-Start Delay Example Diagram

Table 4-7. ASP Channel Controls

Channel

Resolution

MSB Location

LSB Location

ASP Receive DAI0 Channel 1 ASP_RX0_CH1_RES ASP_RX0_CH1_BIT_ST_MSB ASP_RX0_CH1_BIT_ST_LSB

ASP Receive DAI0 Channel 2 ASP_RX0_CH2_RES ASP_RX0_CH2_BIT_ST_MSB ASP_RX0_CH2_BIT_ST_LSB

SCLK

LRCK

Falling

Edge

Rising

Edge

FSYNC_PERIOD

FSYNC_PULSE_WIDTH

SCLK

LRCK

Falling

Edge

Rising

Edge

FSYNC_PERIOD

FSYNC_PULSE_WIDTH

Even FSYNC_PERIOD

Odd FSYNC_PERIOD

FSYNC_PERIOD count clock is absent

FSYNC_PULSE_WIDTH

...

LRCK

Channel location and size

SDIN

FSD = 000

FSD = 001

FSD = 010

N – 1

N – 2

N – 3

N – 4

N – 5

FSD = 011

SCLK

FSD = 100

0.5

1.5

2.5

FSD = 101

End of frame

...

678

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