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ST10F166 데이터시트(PDF) 42 Page - STMicroelectronics |
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ST10F166 데이터시트(HTML) 42 Page - STMicroelectronics |
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42 / 62 page ![]() 42/62 ST10F166 18.5 Testing Waveforms Figure 11. Input Output Waveforms Figure 12. Float Waveforms 18.6 Memory Cycle Variables The timing tables below use three variables which are derived from registers SY- SCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be comput- ed. AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at V IH min for a logic ‘1’ and VIL max for a logic ‘0’. For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a100 mV change from the loaded V OH/VOL level occurs (I OH/IOL = 20 mA). Description Symbol Values ALE Extension t A TCL * <ALECTL> Memory Cycle Time Waitstates t C 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>) |
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