NCV7728DPAR2G datasheet(19/27 Pages) ONSEMI

19 / 27 page

NCV7728

www.onsemi.com

Figure 17. SPI Data Recognition and Frame Detection

SCLK

CSB

Word B – 8 bits

Word A – 16 bits

24 bit Frame

Modulo16 counter begins on the first rising SCLK edge after CSB goes low

SI data is recognized on the falling SCLK edge

SO data is shifted out on the rising SCLK edge

TSD

MSB

LSB

MSB

LSB

Modulo16 counter ends– 16 bit word length valid

Modulo8 counter begins on the next rising SCLK edge

Modulo8 counter ends– 8 bit word length valid

. Valid n*8 bit frame.

The TSD bit is multiplexed with the SPI SO data and OR’d

with the SI input (Figure 18) to allow for reporting in a serial

daisy chain configuration in devices with the same SPI

protocol. A TSD error bit as a “1” automatically propagates

through the serial daisy chain circuitry from the SO output

of one device to the SI input of the next. This is shown in

Figures 19 and 20; first as the daisy chained devices

connected with no thermal shutdown latched fault

(Figure 19) and subsequently with a TSD fault in device 1

propagating through to device 2 (Figure 20).

TSD

SPI

TSD

NCV7718

TSD

NCV7718

“0”

Device #1

Device #2

Figure 18. TSD SPI Link

Figure 19. Daisy Chain No TSD Fault

TSD

NCV7718

TSD

NCV7718

“0”

“1”

“0”

“1”

Device #1

Device #2

Figure 20. Daisy Chain TSD Error

Propagation

NCV7728DPAR2G 데이터시트(PDF) 19 Page - ON Semiconductor

NCV7728DPAR2G 데이터시트(HTML) 19 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

데이터시트 다운로드

링크 URL