AT89C51ED2-RDTIM datasheet(14/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Port Types

AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out-

put that is common on the 80C51 and most of its derivatives. This output type can be

used as both an input and output without the need to reconfigure the port. This is possi-

ble because when the port outputs a logic high, it is weakly driven, allowing an external

device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink

a fairly large current. These features are somewhat similar to an open drain output

except that there are three pull-up transistors in the quasi-bidirectional output that serve

different purposes. One of these pull-ups, called the "weak" pull-up, is turned on when-

ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small

current that will pull the pin high if it is left floating. A second pull-up, called the "medium"

pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is

also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidi-

rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an

external device, the medium pull-up turns off, and only the weak pull-up remains on. In

order to pull the pin low under these conditions, the external device has to sink enough

current to overpower the medium pull-up and take the voltage on the port pin below its

input threshold.

The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up

low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from

a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two

CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all

ports when latch data is logical 0.

The quasi-bidirectional port configuration is shown in Figure 3.

Figure 3. Quasi-Bidirectional Output

2 CPU

Input

Strong

Medium

Weak

Clock Delay

Port Latch

Data

DPU

AUXR.7

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