Integrated

Circuit

Systems, Inc.

ICS9DB106

Preliminary Product Preview

0833A—07/26/04

Pin Configuration

Recommended Application:

1-to-6 Zero-delay or fanout buffer for PCI Express

Output Features:

•

6 - 0.7V current mode differential output pairs (HSCL)

•

SMBus for complete device control

Key Specifications:

•

Cycle-to-cycle jitter < 40ps

•

Output-to-output skew < 30 ps

Features/Benefits:

•

CLKREQ# pin for outputs 1 and 4/output enable for

Express Card applications

•

PLL or bypass mode/PLL can dejitter incoming clock

•

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

•

Spread Spectrum Compatible/tracks spreading input

clock for low EMI

•

SMBus Interface/unused outputs can be disabled

6 Output PCI Express* Buffer with CLKREQ# Function

28-pin SSOP & TSSOP

PLL_BW 1

28 VDDA

CLK_INT 2

27 GNDA

CLK_INC 3

26 IREF

*CLKREQ1# 4

25 **CLKREQ4#

PCIEXT0 5

24 PCIEXT5

PCIEXC0 6

23 PCIEXC5

VDD 7

22 VDD

GND 8

21 GND

PCIEXT1 9

20 PCIEXT4

PCIEXC1 10

19 PCIEXC4

PCIEXT2 11

18 PCIEXT3

PCIEXC2 12

17 PCIEXC3

VDD 13

16 VDD

SMBDAT 14

15 SMBCLK

Note:

Pins preceeded by '**' have internal 120K ohm pull down resistors

*Other names and brands may be claimed as the property of others.

PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to

change without notice.