WM8950 datasheet(35/52 Pages) WOLFSON

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Preliminary Technical Data

WM8950

PTD Rev 2.1 June 2005

A-law Companding

100

120

0.2

0.4

0.6

0.8

Normalised Input

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Figure 22 A-Law Companding

AUDIO SAMPLE RATES

The WM8950 sample rate for the ADC is set using the SR register bits. The cutoffs for the digital

filters and the ALC attack/decay times stated are determined using these values and assume a

256fs master clock rate.

If a sample rate that is not explicitly supported by the SR register settings is required then the

closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,

decay and hold times will scale appropriately.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Table 28 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8950 has an on-chip phase-locked loop (PLL) circuit that can be used to:

Generate master clocks for the WM8950 audio functions from another external clock, e.g. in

telecoms applications.

Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from

an existing audio master clock.

Figure 23 shows the PLL and internal clocking arrangment on the WM8950.

The PLL can be enabled or disabled by the PLLEN register bit.

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