WM8950 datasheet(32/52 Pages) WOLFSON

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WM8950

Preliminary Technical Data

PTD Rev 2.1 June 2005

When using ADCLRSWAP = 1 in DSP/PCM mode, the data will appear in the Right Phase of the

FRAME, which will be 16/20/24/32 bits after the FRAME pulse.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADCLRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of FRAME clock:

0=ADC data appear in ‘left’ phase of

FRAME

1=ADC data appears in ‘right’ phase of

FRAME

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I

2S format

11= DSP/PCM mode

6:5

Word length

00=16 bits

01=20 bits

10=24 bits

11=32 bits (see note)

Frame clock polarity

0=normal

1=inverted

FRAMEP

DSP Mode – mode A/B select

1 = MSB is available on 1st BCLK rising

edge after FRAME rising edge (mode B)

0 = MSB is available on 2nd BCLK rising

edge after FRAME rising edge (mode A)

Audio interface

control

BCP

BCLK polarity

0=normal

1=inverted

Table 24 Audio Interface Control

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below. Each audio interface can be controlled individually.

and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with

BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses

at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.

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