| 전자부품 데이터시트 검색엔진 |
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WM9714CLGEFL/V 데이터시트(PDF) 76 Page - Cirrus Logic |
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WM9714CLGEFL/V 데이터시트(HTML) 76 Page - Cirrus Logic |
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76 / 120 page ![]() WM9714L 76 Rev 4.0 POWER MANAGEMENT INTRODUCTION The WM9714 L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register Powerdown registers 3Ch and 3Eh. Each particular circuit block is active when both the relevant bit in register 26h AND the relevant bit in the Powerdown registers 3Ch and 3Eh are set to ‘0’. Note that the default power-up condition is all OFF. AC97 CONTROL REGISTER REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 26h Powerdown/ Status register 14 PR6 1 (disabled) Output PGAs Disable Control 1 = Disabled 0 = Enabled 13 PR5 1 (disabled) Internal Clock Disable Control 1 = Disabled 0 = Enabled 12 PR4 1 (disabled) AC-Link Disable Control 1 = Disabled 0 = Enabled 11 PR3 1 (disabled) Analogue Disable Control 1 = Disabled 0 = Enabled Note: This control disables VREF, input PGAs, DACs, ADCs, mixers and outputs 10 PR2 1 (disabled) Input PGAs and Mixers Disable Control 1 = Disabled 0 = Enabled 9 PR1 1 (disabled) Stereo DAC Disable Control 1 = Disabled 0 = Enabled 8 PR0 1 (disabled) Stereo ADC and Record Mux Disable Control 1 = Disabled 0 = Enabled 3 REF 0 VREF Ready (Read Only) 1 = VREF ready 0 = VREF not ready 2 ANL 0 Analogue Mixers Ready (Read Only) 1 = Analogue mixers ready 0 = Analogue mixers not ready 1 DAC 0 Stereo DAC Ready (Read Only) 1 = DAC ready 0 = DAC not ready 0 ADC 0 Stereo ADC Ready (Read Only) 1 = ADC ready 0 = ADC not ready Table 59 Powerdown and Status Register (Conforms to AC’97 Rev 2.2) |
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