WM9714CLGEFLSLASHV datasheet(21/120 Pages) CIRRUS

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WM9714L

Rev 4.0

AUXADC

The clock for the AUXADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the

clock generator is set by PENDIV. This enables the AUXADC clock frequency to be set according to

power consumption and conversion rate considerations.

Clock mode and division ratios are controlled by register 44h as shown in Table 3.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

44h

14:12

SEXT[6:4]

000 (div 1)

Defines clock division ratio for Hi-fi:

DSP, ADCs and DACs

000: f

001: f/2

...

111: f/8

11:8

SEXT[3:0]

0000 (div 1)

Defines clock division ratio for PCM

interface and voice DAC in external clock

mode only:

0000: f

0001: f/2

…

1111: f/16

CLKSRC

1 (ext clk)

Selects between PLL clock and External

clock

0: PLL clock

1: external clock

5:3

PENDIV

000 (div 16)

Sets AUXADC clock divisor

000: f/16

001: f/12

010: f/8

011: f/6

100: f/4

101: f/3

110: f/2

111: f

CLKBX2

0 (Off)

Clock doubler for MCLKB

CLKAX2

0 (Off)

Clock doubler for MCLKA

CLKMUX

0 (MCLKA)

Selects between MCLKA and MCLKB

(N.B. On power-up clock must be present

on MCLKA and must be active for 2 clock

cycles after switching to MCLKB)

0: SYSCLK=MCLKA

1: SYSCLK=MCLKB

Table 3 Clock Muxing and Division Control

PLL MODE

The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation:



Integer N



Fractional N

The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz

–

19.661MHz (LF=0) and 2.048MHz

– 4.9152MHz (LF=1). Through use of a clock divider (div by 2 / 4)

on the input to the PLL frequencies up to 78.6MHz can be accommodated. The input clock divider is

enabled by DIVSEL (0=Off) and the division ratio is set by DIVCTL (0=div2, 1=div4).

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