AD9544SLASHPCBZ datasheet(28/62 Pages) AD

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AD9544

Data Sheet

Rev. 0 | Page 28 of 62

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

SYSTEM CLOCK INPUTS

XOA

XOB

AD9544

25MHz TO 60MHz

FUNDAMENTAL

AT-CUT CRYSTAL

CTUNE

Figure 23. System Clock Input (XOA/XOB) in Crystal Mode

(Each CTUNE Shunt Capacitor Shown Must Equal 2× (CLOAD − CSTRAY,

Where Typical CSTRAY = 2 pF to 5 pF)

XOA

330Ω

150Ω

0.1µF

XOB

AD9544

3.3V

CMOS

TCXO

0.1µF

Figure 24. System Clock Input (XOA, XOB) when Using a TCXO/OCXO with

3.3 V CMOS Output

REFERENCE CLOCK INPUTS

REFx

REFxx

INTERNAL DC THRESHOLD

FOR 1.2V OR 1.8V CMOS

AD9544

1.8V RECEIVER

CMOS

DRIVER

HI-Z

INPUT

Figure 25. Single-Ended DC-Coupled Mode, 1.2 V or 1.8 V CMOS

(OPTIONAL)

0.1µF

REFx

REFxx

AD9544

1.8V RECEIVER

DRIVER

1.2V

47kΩ

0.6V

Figure 26. Single-Ended AC-Coupled Mode

REFx

REFxx

AD9544

DRIVER

1.2V

47kΩ

0.6V

Figure 27. Single-Ended Internal Pull-Up Mode

REFx

LVDS DRIVER

(1.2V COMMON-MODE)

REFxx

AD9544

100Ω

20µA

1.2V

30kΩ

LEVEL SHIFT

Figure 28. Differential LVDS Input Mode

REFx

DIFFERENTIAL

DRIVER

REFxx

AD9544

47Ω

0.6V

0.1µF

1.2V

0.6V

47Ω

Figure 29. Differential AC-Coupled Mode (RL = 100 Ω Is Recommended,

Except For HCSL)

REFx

DIFFERENTIAL DRIVER

(0.6V COMMON-MODE)

REFxx

AD9544

Figure 30. Differential DC-Coupled Mode

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