DAC5686IPZP datasheet(42/46 Pages) TI

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IOUT1

1:1

IOUT2

Ω

RLOAD

Ω

100

Ω

AVDD (3.3 V)

IOUT1

4:1

IOUT2

100

Ω

100

Ω

RLOAD

Ω

AVDD (3.3 V)

SLEEP MODE

POWER-UP SEQUENCE

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

Figure 48. Driving a Doubly Terminated 50-

Ω Cable Using a 1:1 Impedance-Ratio Transformer

Figure 49. Driving a Doubly Terminated 50-

Ω Cable Using a 4:1 Impedance-Ratio Transformer

The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to

less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of –40

°C to 85°C. The power-down

mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An

internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected.

Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a

nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up.

In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or

simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order.

Within AVDD, the multiple AVDD pins should be powered simultaneously.

DAC5686IPZP 데이터시트(PDF) 42 Page - Texas Instruments