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DAC5686IPZP 데이터시트(PDF) 26 Page - Texas Instruments |
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DAC5686IPZP 데이터시트(HTML) 26 Page - Texas Instruments |
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26 / 46 page ![]() www.ti.com Dual-Bus Mode IOUTB1 IOUTB2 IOUTA1 IOUTA2 16-Bit DAC DA[15:0] DB[15:0] 2Fdata 2 – 16 y Fdata Fdata y2 16-Bit DAC 2Fdata y2 FIR1 Edge Triggered Input Latches • •• • •• DEMUX CLK1 DA[15:0] DB[15:0] ts(DATA) th(DATA) A0 A1 A2 AN AN+1 A3 B0 B1 B2 BN BN+1 B3 CLK2 DA[15:0] DB[15:0] ts(DATA) th(DATA) A0 A1 A2 AN AN+1 A3 B0 B1 B2 BN BN+1 B3 PLLLOCK td(PLLLOCK) DAC5686 SLWS147B – APRIL 2003 – REVISED AUGUST 2004 In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 28 shows the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 29 for the PLL clock mode and in Figure 30 for the external clock mode. Figure 28. Dual-Bus Mode Data Path Figure 29. Dual-Bus Mode Timing Diagram (PLL Mode) Figure 30. Dual-Bus Mode Timing Diagram (External Clock Mode) 26 |
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