DAC5686IPZP datasheet(22/46 Pages) TI

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R/W

tSCLKL

SDENB

SCLK

SDIO

N1 N0

−

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDENB

SCLK

SDIO

Instruction Cycle

Data Transfer Cycle(s)

ts(SDENB)

tSCLK

th(SDIO)

ts(SDIO)

tSCLKH

R/W

SDENB

SCLK

SDIO

N1 N0

−

A3 A2 A1 A0

D6 D5 D4 D3 D2

D0 0

Instruction Cycle

Data Transfer Cycle(s)

SDO

D7 D6 D5 D4 D3 D2 D1 D0 0

3-Pin Configuration

Output

4-Pin Configuration

Output

SDENB

SCLK

SDIO

Data n

Data n−1

SDO

td(Data)

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

Figure 24. Serial-Interface Write Timing Diagram

Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface

clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial

data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the

data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from

the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin

configuration.

Figure 25. Serial-Interface Read Timing Diagram

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