SCD1284 datasheet(38/176 Pages) INTEL

38 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

For transmit and modem service-acknowledge cycles, the data in the lower three bits is redundant

to the software because the corresponding acknowledge has occurred. These bits are important in

the case of a serial receive-data service acknowledge because they provide an indication of whether

the request is for ‘good’ data or exception data. They are important to the parallel port because they

indicate if the state-machine or data pipeline (or both) are requesting service.

The value contained in the upper five bits of the LIVR can be used for a number of purposes. The

primary purpose of the LIVR is as a source of a software vector used by the system as an index into

a interrupt dispatch table. However, systems that cannot use this or do not need it can use these bits

for any purpose. In multiple–CD1284 designs that use daisy-chaining, a logical value to place in

these bits is a chip identification number. This is detailed in the daisy-chaining description in

Section 5.3.4.

Figure 5. Control Signal Generation

Table 14. Request-Type Bit Assignments

Bit 2

Bit 1

Bit 0

Request Type

Not used

Group 1: Modem signal change service request

Group 2: Transmit data service request

Group 3: Received good data service request

Parallel port state-machine requests service (refer to Section 5.4)

Parallel port data pipeline request service (refer to Section 5.4)

Both the parallel port state-machine and data pipeline request service (refer to

Section 5.4)

Group 3: Received exception data service request

SVCACKR*

SVCACKT*

SVCACKM*

DGRANT*

CD1284

CS*

R/W*

DS*

AD[6:0]

DB[7:0]

SVCACKP*

CPU

ADDRESS

CPU I/O

CONTROL

ADDRESS

DECODE

LOGIC

CPU

DATA

SCD1284 데이터시트(PDF) 38 Page - Intel Corporation

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