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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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NUC505-YO2G 데이터시트(PDF) 96 Page - Nuvoton Technology Corporation |
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NUC505-YO2G 데이터시트(HTML) 96 Page - Nuvoton Technology Corporation |
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96 / 130 page  NUC505 July. 26, 2018 Page 96 of 130 Rev.1.08 6.11.2 Features The NUC505 series provides two channels of I 2C. The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include: Master/Slave mode and General Call Mode Bidirectional data transfer between masters and slaves Multi-master bus Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to stretch and un-stretch serial transfer Built-in a 14-bit time-out counter will request the I 2C interrupt if the I2C bus hangs up and time-out counter overflows. Programmable divider allowing for versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) Supports address match wake-up function |
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