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NUC505-YO2G 데이터시트(PDF) 118 Page - Nuvoton Technology Corporation

부품명 NUC505-YO2G
상세설명  ARM짰 Cortex짰-M4 32-bit Microcontroller
PDF  130 Pages
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제조업체  NUVOTON [Nuvoton Technology Corporation]
홈페이지  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC505-YO2G 데이터시트(HTML) 118 Page - Nuvoton Technology Corporation

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NUC505
July. 26, 2018
Page 118 of 130
Rev.1.08
7.4.7
I
2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min.
Max.
Min.
Max.
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH
SCL high period
4
-
0.6
-
uS
tSU; STA
Repeated
START
condition
setup time
4.7
-
1.2
-
uS
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
STOP condition setup time
4
-
0.6
-
uS
tBUF
Bus free time
4.7[3]
-
1.2[3]
-
uS
tSU;DAT
Data setup time
250
-
100
-
nS
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus
line
-
400
-
400
pF
Notes:
1.
Guaranteed by design, not tested in production.
2.
HCLK must be higher than 2 MHz to achieve the maximum standard mode I
2C frequency. It must be
higher than 8 MHz to achieve the maximum fast mode I
2C frequency.
3.
I
2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
5.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the
low period of SCL signal.
tBUF
STOP
SDA
SCL
START
tHD;STA
tLOW
tHD;DAT
tHIGH
tf
tSU;DAT
Repeated
START
tSU;STA
tSU;STO
STOP
tr
Figure 7.4-2 I
2C Timing Diagram



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