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DSM2180F3 데이터시트(PDF) 35 Page - STMicroelectronics |
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DSM2180F3 데이터시트(HTML) 35 Page - STMicroelectronics |
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35 / 63 page ![]() 35/63 DSM2180F3 Table 16. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Figure 20. Port B Structure Port B – Functionality and Structure Port B can be configured to perform one or more of the following functions: s MCU I/O Mode s CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port B. McellBC7- McellBC0 can be connected to Port B or Port C. s CPLD Input – Via the Input Macrocells (IMC). s Open Drain/Slew Rate – pins PB3-PB0 can be configured to fast slew rate, pins PB7-PB4 can be configured to Open Drain Mode. Drive Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port B Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Port C Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port D NA1 NA1 NA1 NA1 NA1 Slew Rate Slew Rate Slew Rate DATA OUT REG. DQ DQ WR WR MACROCELL OUTPUTS ENABLE PRODUCT TERM (.OE) READ MUX P D B CPLD - INPUT DIR REG. Input Macrocell ENABLE OUT DATA IN OUTPUT SELECT OUTPUT MUX PORT B PIN DATA OUT AI04906B |
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