전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

CS42406 데이터시트(PDF) 21 Page - Cirrus Logic

부품명 CS42406
상세설명  24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC
PDF  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42406 데이터시트(HTML) 21 Page - Cirrus Logic

Back Button CS42406 Datasheet HTML 17Page - Cirrus Logic CS42406 Datasheet HTML 18Page - Cirrus Logic CS42406 Datasheet HTML 19Page - Cirrus Logic CS42406 Datasheet HTML 20Page - Cirrus Logic CS42406 Datasheet HTML 21Page - Cirrus Logic CS42406 Datasheet HTML 22Page - Cirrus Logic CS42406 Datasheet HTML 23Page - Cirrus Logic CS42406 Datasheet HTML 24Page - Cirrus Logic CS42406 Datasheet HTML 25Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 50 page
background image
CS42406
21
SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT (Logic “0” = GND =
0 V, Logic “1” = VLS)
* For a description of Speed Modes, please refer to Section 4.1.2 on page 30.
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Specifications
MCLK Frequency
1.024
-
12.8
MHz
22
-
25.6
MHz
MCLK Duty Cycle
45
-
55
%
Single-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
128
×Fs
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns
Double-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
64
×Fs
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns
Quad-Speed*
DAC_LRCK Duty Cycle
45
-
55
%
DAC_SCLK Frequency
-
-
MCLK/2
Hz
DAC_SCLK Pulse Width Low
tsclkl
20
-
-
ns
DAC_SCLK Pulse Width High
tsclkh
20
-
-
ns
DAC_SCLK rising to DAC_LRCK edge delay
tslrd
20
ns
DAC_SCLK rising to DAC_LRCK edge setup time
tslrs
20
ns
SDINx valid to DAC_SCLK rising setup time
tsdlrs
20
ns
DAC_SCLK rising to SDINx hold time
tsdh
20
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com