M65818AFP datasheet(37/39 Pages) RENESAS

37 / 39 page

M65818AFP

Rev.1.00, Sep.04.2003, page 37 of 38

8. Application Example

M65818AFP

LRCK

BCK

DATA

XfsiIN

(Primary Side Clock)

OUTL1+

OUTL1-

OUTL2+

OUTL2-

OUTR1+

OUTR1-

OUTR2+

OUTR2-

NSPMUTE

SCDT

SCSHIFT

SCLATCH

PGMUTE

INIT

XFsoIN

(Secondary Side Clock)

MCKSEL

DSP

MCU

DSD128FS

DSD64Fs

DSDR

DSDL

SACD

Decoder

External 8fs Data

Input: External Sampling

Rate Converter

Output: External DAC

External 8FsData Input/Output Setting

L: Input

H: Output

DSDCKSEL1

DSDCKSEL2

DSDCKIO

Set Timing 1

SACD Interface

Select shift clock I/O for DSD

L: Input

H: Output

MODE1

MODE2

Set Input Mode1

FsoCKO

FsoI

Clock for a secondary side synchronization

(for Multi channel use)

Set Secondary Clock

L:1024Fso H:512Fso

CKCTL1

CKCTL2

CKOUT1

CKOUT2

CKOUT3

Set Secondary Clock 1

SYNC

Re-Synchronization

Flag Output

XFsoOUT

FsiI

(Clock for a primary side synchronization)

Oscillator

Power

Driver

Initialize

Mute Input

Secondary Clock Output 1

Set Timing 2

SACD Interface

Set Input Mode 2

Secondary Clock Output 2

Secondary Clock Output 3

Secondary Clock Output

Power

Driver

Set Secondary Clock 2

M65818AFP 데이터시트(PDF) 37 Page - Renesas Technology Corp

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