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M65818AFP 데이터시트(PDF) 14 Page - Renesas Technology Corp

부품명 M65818AFP
상세설명  Digital Amplifier Processor of S-Master Technology
PDF  39 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M65818AFP 데이터시트(HTML) 14 Page - Renesas Technology Corp

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M65818AFP
Rev.1.00, Sep.04.2003, page 14 of 38
Setting of DSDCKIO is following table.
DSDCKIO
Selection of DSD64fs and DSD128fs I/O
L
Input mode
H
Output mode
• SACD Input Format
mode1
DSDL/R (input data)
DSD128fs
DSD64fs
mode2
DSDL/R (input data)
DSD128fs
DSD64fs
mode3
DSDL/R (input data)
DSD128fs
DSD64fs
mode4
DSDL/R (input data)
DSD128fs
DSD64fs
* D0:Positive phase data,
XD0:Negative phase data (reversal)
Positive phase data are fetched at the timing of "O" marks in upper figure.
D3
XD3
D0
XD0
D1
XD1
D2
XD2
128fs
64fs
D0
XD0 D1
XD1 D2
XD2
D3
XD3
128fs
64fs
D0
D1
D2
D3
64fs
D3
XD3
D0
XD0
D1
XD1 D2
XD2
128fs
64fs
5.6. MCKCEL, XfsoIN, XfsoOUT
32 28 77
XfsoIN pin is secondary master clock input.
The state of MCKSEL pin selects secondary master clock.
MCKSEL
XfsoIN
L
1024fso
H
512fso
XfsoOUT pin is buffered-output from XfsoIN pin's input clock.



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