S1M8822X01-R0T0 datasheet(6/22 Pages) SAMSUNG

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S1M8821/22/23

INTERGER RF/IF DUAL PLL

PIN DESCRIPTION

Pin No

(20TSSOP)

Pin No

(24QFN)

Symbol

I / O

Description

124

VDD1

Power supply voltage input for the RF PLL part. VDD1 must

equal VDD2. In order to reject supply noise, bypass capacitors

must be placed as close as possible to this pin and be

connected directly to the ground plane.

N/C

No connection.

Vp1

Power supply voltage input for RF charge pump(

≥ VDD1).

CPoRF

Internal RF charge pump output for connection to an external

loop filter whose filtered output drives an external VCO.

GND

Ground for RF digital blocks.

finRF

RF prescaler input. The signal comes from the external VCO.

finRF

The complementary input of the RF prescaler. A bypass

capacitor must be placed as close as possible to this pin and

be connected directly to the ground plane. The bypass

capacitor is optional with some loss of sensitivity.

GND

Ground for RF analog blocks.

OSCin

Reference counter input. TCXO is connected via a coupling

capacitor.

N/C

No connection.

GND

Ground for IF digital blocks.

foLD

Multiplexed output of the RF/IF programmable counters, the

reference counters, the lock detect signals and the shift

registers. The output level is CMOS level. (see fout

Programmable Truth Table)

CLOCK

CMOS clock input. Serial data for the various counters is

transferred into the 22-bit shift register on the rising edge of

the clock signal.

N/C

No connection.

DATA

Binary serial data input. The MSB of CMOS input data is

entered first. The control bits are on the last two bits. CMOS

input.

Load enable CMOS input. When LE becomes high, the data

in the shift register is loaded into one of the four latches (by

the control bits).

GND

Ground for IF analog blocks.

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