INTERGER RF/IF DUAL PLL

S1M8821/22/23

13

FUNCTIONAL DESCRIPTION

The Samsung S1M8821/22/23 are dual PLL frequency synthesizer ICs. S1M8821/22/23 combined with external

LPFs and external VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter,

prescaler, phase detector, charge pump, and etc.

Serial data is moved into 20-bit shift register on the rising edge of the clock. These data enters MSB first. When LE

becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control). The divide ratios of

the prescaler and the counters are determined by the data stored in the latches. The external VCO output signal is

divided by the prescaler and the N counter. External reference signal is divided by the R counter. These two signals

are the two input signals to the phase detector. The phase detector drives the charge pump by comparing

frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage

for the external VCO and finally the VCO generates the appropriate frequency signal.

Serial Data Input Timing

MSB

LSB

N20(R20)

N19(R19)

N10(R10)

N9(R9)

C2

C1

DATA

CLOCK

LE